A phase-locked loop (PLL) generally includes a voltage control oscillator (VCO), a phase frequency detector (PFD), a frequency divider, a charge pump and a loop filter, and has a phase-locking function for locking the output signal of the VCO to a reference input signal. All components influence the performance of the overall circuit, but the VCO is the element that decides the operating frequency of the PLL; thus the VCO is most influential on PLL performance. That is, the highest and lowest frequencies of the VCO restrict the tuning range of frequency in the PLL. In addition, the change in output magnitude of the VCO within the tuning range should be substantially minimized, and jitter noise should be also substantially reduced.
In the VCO, a typical ring oscillator is configured with an inverter chain in which terminals are connected in series, and a final output terminal in the chain is connected to the first input terminal. In another configuration, the VCO is configured in a differential amplifier type in which a final output is cross-fed to an input and includes a configuration of even-number stages.
In an inverter chain type ring oscillator, an inverter having a simplified structure is used as a delay element; thus power consumption is relatively low and, at the same time, a high oscillation frequency can be obtained. However, when the oscillation frequency of ring oscillator is increased, influence from a variation in operating temperature, a variation in power source voltage, and a variation in process parameters, is increased. A differential amplifier type ring oscillator, on the other hand, has a relatively complicated configuration, but is strongly isolated from the influence of external noise.
In the inverter chain type ring oscillator, the principle of the oscillation operation is closely related to the inverting function and the delay function as characteristics of inverters. For example, in configuring a ring oscillator with an odd number of inverter stages, when an input of logic 1 is applied to a first stage, an output of the first stage becomes logic 0 after a lapse of a given delay time, and again after a lapse of given delay time, an output of second stage becomes logic 1. Thus, if the propagation delay time of an inverter is Td and the ring oscillator includes N inverters, N being an odd number; the time elapsed when an inverted signal of a first input is applied again as a first input, becomes NTd, and signals of the ring oscillator represented by repeating cycles of the above procedure become periodic signals. That is, an oscillation period of a ring oscillator having N inverters with a delay time of Td, becomes 2NTd.
To realize a ring oscillator constructed of differential amplifiers based on an even number of stages, an input of the first stage and an output of the final stage are cross-connected with each other. When logic signals of 1 and 0 are each input to an input terminal of first differential amplifier, output signals of the final stage become logic 0 and logic 1. At this time, the output of the final stage is also connected to an input of the first stage, thus in a differential ring oscillator constructed of the N-number of differential amplifiers, N being an even number, an input of first differential amplifier is inverted after a lapse of NTd. Then, an oscillation period of differential ring oscillator constructed of N even-number stages becomes 2NTd as in the case of the ring oscillator of odd-number of stages.
A conventional ring oscillator employed in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) etc. has a period that varies greatly in response to variations in the power source voltage Vcc level and temperature level. In particular, the period is reduced in a high voltage (high Vcc) or low temperature environment, and is increased in a low voltage (low Vcc) or high temperature environment. Such a ring oscillator may be used in the DRAM to control a refresh period of the device.
A conventional ring oscillator circuit is described as follows. Recently, a ring oscillator PLL has become popular by employing a differential amplifier circuit. In a differential amplifier type ring oscillator PLL, to perform an oscillation with a phase shift (phase delay) of 90 degrees and a sufficient output gain, the parasitic capacitance of the circuit should be appropriately controlled. However, the control of parasitic capacitance has a limitation related to the Miller effect, and is difficult to precisely predict. A magnitude difference of two poles becomes greater by the Miller effect; thus, obtaining a sufficient phase shift is difficult.
In a more improved conventional design, the structure of FIG. 1 to solve problems caused in the ring oscillator realized by using differential amplifiers and to reduce current consumption and jitter generation, is well known in the field. FIG. 1 is a block diagram of a conventional ring oscillator, and FIG. 2 is a circuit diagram illustrating in detail a differential amplifier constituting a portion of the ring oscillator of FIG. 1.
As shown in FIG. 1, a conventional ring oscillator according to the prior art has a mutually cross-connected configuration of two stages including a first differential amplifier 31 and a second differential amplifier 32, in which a unit differential amplifier is configured as shown in FIG. 2. A load terminal of the differential amplifier is constructed of an active load that operates as an inductor by a frequency characteristic graph. In other words, an output terminal Vz and an output terminal Vzb of the first and second differential amplifiers 31 and 32 are cross coupled, and an output node Vob and an output node Vo are used as an output terminal operating as a low pass filter.
Referring to FIG. 2, a differential amplifier includes a first PMOS (P-channel Metal Oxide Semiconductor) transistor 41 for supplying power source voltage to a drain in response to a bias voltage Vbiasp applied through a gate; second and third PMOS transistors 42 and 43, of which sources are each connected to a drain of the first PMOS transistor 41, and which receive an input signal Vi and an input signal Vib at gates thereof; cross-coupled first-stage transistors 46 configured between a drain of the second PMOS transistor 42 and a ground terminal; a first oscillator Cz, 44 configured between an output node Vzb and a ground terminal; a resistance Rz configured between the output node Vzb and a cross-coupling node Vob; cross-coupled second-stage transistors 47 configured between a drain of the third PMOS transistor 43 and a ground terminal; a second oscillator Cz, 45 configured between an output node Vz and a ground terminal; and a resistance Rz configured between a node Vz and a cross-coupling node Vo.
In the circuit structure of the differential amplifier shown in FIG. 2, a phase shift of 90 degrees can be obtained regardless of the value of capacitance Cz. That is, in the circuit configuration of FIG. 1 where differential amplifiers of FIG. 2 are connected in two stages and an output terminal different from the existing output terminal is used in the mutually connected structure, the phase shift of 90 degrees necessary for an oscillation of ring oscillator can be obtained regardless of the size of the load transistor. Output gain is improved by using the cross-coupled transistor configuration that is added to prevent a reduction of the output gain. In the configuration of FIG. 2, the output terminal Vz, Vzb operates as a low pass filter to a variation in power supply; thus, jitter can be mitigated.
The configuration of FIG. 1 operates to overcome the limited oscillation condition of the two-stage ring oscillator, and has a modified structure in the output terminal so as to increase the phase shift level of the ring oscillator.
However, in the circuit of FIG. 2, resistance values of the resistors Rz between node Vzb and the cross-coupling node Vob and of the resistor Rz between node Vz and the cross coupling node Vo are fixed, thus the resonance frequency response is relatively small. Hence, the resonance lowest voltage is relatively high, and so it is difficult to ensure a resonance frequency response of a desired larger range in the ring oscillator.
Further, an externally applied power source voltage is used as the operating power source voltage; thus when the external power source voltage includes noise, jitter characteristics of the circuit can be adversely affected.